Digital receiver

ABSTRACT

A digital receiver, comprising: a frequency converter ( 100, 101, 102, 103, 104, 105 ) arranged to convert a received signal into baseband signals; delay units ( 106, 107 ) arranged to delay the baseband signals to provide delayed signals; normalizing means ( 108 ) arranged to truncate the baseband signals and the delayed signals to a predetermined length and provide normalized signals; a demodulator ( 109 ) arranged to demodulate the normalized signals and provide a demodulated signal; and frequency offset sensing means ( 110 ) arranged to sense an envelope of the demodulated signal to provide an offset signal indicative of a frequency offset of the received signal.

FIELD OF THE INVENTION

[0001] The present invention relates to a digital receiver suitable foruse in a Burst-mode communication system.

BACKGROUND OF THE INVENTION

[0002] Low power consumption, cost-reduction, and compact size are someof the key features of a mobile/personal communication system such asGSM, DECT and Bluetooth based systems. Full integration is a veryimportant way to reduce cost and size. The zero-IF receiver can beimplemented in a highly integrated way. However, it suffers from dcoffset, self-mixing, and mismatch between the different downconversionpaths. The use of zero-IF is limited due to its poor performance.Although the conventional IF (heterodyne) receiver can achieve goodperformance, its implementation needs many off-chip components, whichmakes it vulnerable, expensive, and sensitive to external parasiticsignals. Its power consumption is also increased. Accordingly, a needexists in the art to provide a digital receiver which can be implementedin a highly integrated way while still maintaining high quality signalreception.

SUMMARY OF THE INVENTION

[0003] In accordance with one aspect of the present invention, there isprovided a digital receiver, comprising: a frequency converter arrangedto convert a received signal into baseband signals; delay units arrangedto delay the baseband signals to provide delayed signals; normalizingmeans arranged to truncate the baseband signals and the delayed signalsto a predetermined length and provide normalized signals; a demodulatorarranged to demodulate the normalized signals and provide a demodulatedsignal; and frequency offset sensing means arranged to sense an envelopeof the demodulated signal to provide an envelope signal.

[0004] Typically, the normalizing means is arranged to truncate thebaseband signals and the delayed signals by: selecting from the basebandsignals and the delayed signals one with the largest absolute value;determining a bit position of most significant bit of the selectedsignal; truncating each of the signals to the pre-determined lengthdependent upon the bit position.

[0005] Typically, the frequency offset sensing means comprises: meansarranged to track the envelop of the demodulated signal to provide atracking signal; and filter arranged to low pass filter the trackingsignal to provide the envelope signal.

[0006] An advantage of the present invention is to provide a digitalreceiver suitable to be implemented in the form of an applicationspecific integrated circuit (ASIC) with the specific design features oflow power consumption and small size.

[0007] Another advantage of the present invention is to provide a simplenormalization scheme to truncate a signal without introducingunacceptable distortion.

[0008] Still another advantage of the present invention to provide amethod and apparatus arranged to estimate and compensate effects of thefrequency offset between the transmitter and receiver in the system.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the invention will now be discussed, by way ofexample, with reference to the accompanying drawings in which likereference characters identify correspondingly throughout and wherein:

[0010]FIG. 1 schematically illustrates a first embodiment of a digitalreceiver according to the present invention;

[0011]FIG. 2 schematically illustrates the structure of an analogfront-end of the digital receiver shown in FIG. 1;

[0012]FIG. 3 shows an example of the operation of a normalizer of thedigital receiver of FIG. 1;

[0013]FIG. 4 is a schematic block diagram illustrating the structure ofa demodulator of the digital receiver shown in FIG. 1;

[0014]FIG. 5 is a schematic block diagram illustrating the structure ofa filtering device of the digital receiver shown in FIG. 1;

[0015]FIG. 6 is a flow chart of the algorithm for computing the lowfrequency component caused by the frequency offset in the filteringdevice of FIG. 5;

[0016]FIG. 7 schematically illustrates a second embodiment of a digitalreceiver according to the present invention;

[0017]FIG. 8 is a schematic block diagram illustrating the structure ofa demodulator of the digital receiver shown in FIG. 7;

[0018]FIG. 9 is a schematic block diagram illustrating the structure ofa filtering device of the digital receiver shown in FIG. 7; and

[0019]FIG. 10 is a flow chart of the algorithm for computing the lowfrequency component caused by the frequency offset in the filteringdevice of FIG. 9.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

[0020] A first embodiment of a digital receiver for a burst-modecommunication system is shown in FIG. 1. The receiver 1 includes ananalogue front-end 100 arranged to convert a RF signal received from anantenna into a low IF signal; an AD converter 101 arranged to provideanalogue-to-digital conversion of the output from the analogue front-end100; a pair of mixers 102 and 103, coupled to the output of the ADconverter 101, arranged to mix the AD converted signal with sine andcosine signals respectively to obtain two orthogonal components of thelow IF signal, namely, I′_(n) and Q′_(n); a pair of low pass filter(LPF) 104 and 105, coupled to the pair of mixers, arranged to filterhigh frequency contents of the two orthogonal components to obtain twobaseband orthogonal components, namely, I_(n) and Q_(n); a pair of delayunits 106 and 107, coupled to the pair of LPF 104 and 105, arranged todelay the two baseband orthogonal components I_(n) and Q_(n) by asampling period, T_(s), to obtain two delayed components I_(n-1) andQ_(n-1); a normalizer 108, coupled to the outputs of the pair of LPF 104and 105, as well as the outputs of the pair of delay units 106 and 107,arranged to normalize the four components (i.e., I_(n), Q_(n), I_(n-1)and Q_(n-1)) by truncating them to pre-determined lengths of L bits, toyield four normalized signals, I_(n) ^(tr), I_(n-1) ^(tr), Q_(n) ^(tr)and Q_(n-1) ^(tr); demodulator 109 arranged to demodulate the normalizedsignals from the normalizer 108; a filtering device 110 arranged to lowfrequency filter the demodulated signal x_(n) so as to obtain itsaverage value dc_(n); a decider 111 arranged to decide a tentativesignal {circumflex over (b)}_(n) according to the demodulated signalx_(n) and the average value dc_(n); and a symbol timing recovery 112arranged to recover the symbol timing of the tentative signal{circumflex over (b)}_(n).

[0021] Hereinafter, with reference to FIGS. 2-6, the operations of theanalog front-end 100, normalizer 108, demodulator 109, filtering device110 will be explained.

[0022]FIG. 2 schematically illustrates the structure of the analogfront-end 100 of the digital receiver 1 shown in FIG. 1. The analogfront-end 100 includes a band-pass filter 200 arranged to filter thesignal received from the antenna; a low noise amplifier 201, coveringthe whole bandwidth of the receiver 1, arranged to provide low noiseamplification of the band-pass filtered signal from BPF 200 to suppressout-of block parts of the received signal; a voltage controlledoscillator 202 arranged to generate a local oscillating signal; a mixer203 arranged to mix the amplified signal from LNA 201 with the localoscillating signal from VCO 202 to downconvert the frequency of thereceived signal into a low intermediate frequency (IF); a complexband-pass filter 204, centered at f_(IF), arranged to band-pass filterthe signal from the mixer to suppress its mirror signal; an AGC controlcircuit 205 arranged to detect the strength of the filtered signal fromthe complex band-pass filter 204 and control a gain of the followingamplifier 206; an amplifier 206 arranged to amplify the filtered signalfrom the complex band-pass filter 204 under the gain-control of AGC 205.The above-described analog front end 100 functions to convert thefrequency of the received signal from the antenna from a radio frequencyinto a low intermediate frequency. A low intermediate frequency is anintermediate frequency lower than a conventional intermediate frequency.A low-IF receiver, like a zero-IF receiver, has a multi-path topologysuitable for a highly integrated design to reduce cost and size. It usesan IF frequency of a few hundred kilohertz and is insensitive toparasitic baseband signals, such as dc offset and self-mixing products.The low-IF receiver combines the advantages of both the conventional IFand the zero-IF receivers. It also has a high performance and is highlyintegrable. Moreover, due to use of the complex bandpass filter 204,following the analog front-end 100, only one AD converter is needed foranalog-digital conversion of the low IF signal into a digital signalr_(n) at a fixed sampling frequency f_(s). The output signal r_(n), fromthe AD converter is represented as:

r _(n) =A cos [2π(f _(IF +Δ) _(f))nT _(s)+φ_(n) +θ]+n _(n),   (1)

[0023] where, A is the amplitude of the digital signal, Δ_(f) is thefrequency offset between the transmitter and receiver in the system,which is caused by the discrepancy between the oscillators at thetransmitter and receiver or the Doppler effect, θ is the phase offsetintroduced by the VCO of the receiver, n_(n) and φ_(n) are the nthsamples of white Gaussian noise and the phase of GFSK modulated signalrespectively.

[0024] The low IF signal from the AD 101 is further downconverted into abasedband signal by the pairs of mixers (102, 103) and low pass filters(104 and 105). In the mixers 102 and 103, the digital signals from AD101 are mixed with sine and cosine signals, sin 2πf_(IF)t and cos2πf_(IF)t, respectively, to obtain two orthogonal components, I′_(n) andQ′_(n). After filtering high frequency terms of the two orthogonalcomponents by the pair of LPFs 104 and 105, two orthogonal basebandcomponents (i.e., in-phase and quadrature base band components I_(n) andQ_(n)) are produced as follows:

I _(n) =−A sin [2πΔ_(f) nT _(s)+φ(nT _(s))+θ] Q _(n) =A cos [2πΔ_(f) nT_(s)+φ(nT _(s))+θ]  (2)

[0025] If f_(s)=4f_(IF), then the above sine and cosine signals can besimplified as bit sequences 0,1,0,1 and 1,0,−1,0. This technique greatlysimplifies the design for the mixers, since the mixing of the digitalsignal from AD 101 with the two bit sequences needn't be implemented bymultipliers.

[0026] At the receiver side, the amplitude of its output signal dependson the transmitted signal power, the propagation loss, the fadingenvironment and the AGC. Therefore, the output from the digital receivermay have many bits and the valid signal range may vary due to theaforementioned factors. To minimize the logic size and power consumptionof the receiver, before passing the four components, I_(n), Q_(n) fromthe pair of LPFs and I_(n-1), Q_(n-1) from the pair of delay units, tothe demodulator 109 for further processing, a simple normalizer 108 isadopted to automatically truncate the lengths of these components from Nbits to L bits (L<N). L is experimentally determined so that thetruncation of signals will not degrade the performance of the receivingsystem.

[0027] Referring FIG. 3, an example of the operation of the normalizer108 is discussed in detail. It is assumed that the lengths of the fourcomponents (I_(n), I_(n-1), Q_(n), Q_(n-1)) input into the normalizerare N bits and the lengths of the outputs from the normalizer are Lbits. The four components (I_(n), I_(n-1), Q_(n), Q_(n-1)) are signeddata. The normalization procedure comprises the following steps:

[0028] Find the input with the maximum absolute value from the fourinput components. In this example, the input with the maximum absolutevalue is I_(n-1).

[0029] Determine the bit position of the most significant bit of theinput component having the maximum absolute value. Most significant bitmeans a bit which makes the largest contribution to the absolute valueof binary data. If the binary data is a signed data, the mostsignificant bit is the first bit whose value is different from that ofits sign bit. For I_(n-1), since the value of its sign bit is ‘0’, mostsignificant bit thereof shall be the first bit whose value is ‘1’. FromFIG. 3, it can be seen that the bit position of most significant bit ofI_(n-1) is N-2, and is recorded as i (i=N-2).

[0030] Truncate each of the inputs to a pre-determined length of L bits.In this example, since the four inputs are signed data, their sign bitsremain in their truncated signals. More particularly, the four inputsare truncated by selecting L-1 bits of each input starting from the bitposition determined in the above step, i.e., L-1 bits between the i thand (i-L-2) th bits, and then adding a sign bit of each of the inputs.In the example shown in FIG. 3, the four inputs are truncated byselecting L-1 bits from the (N-2) th bit to the (N-L-4) th bit (i.e.,the fifth bit) and adding the sign bit of each input (i.e., sign bits 0,0, 1 and 1) as a first bit of each truncated signal. The four truncatedsignals I_(n), I_(n-1), Q_(n), Q_(n-1) with the pre-determined length ofL bits are shown on the right side of FIG. 3.

[0031] The truncated data I_(n) ^(tr), I_(n-1) ^(tr), Q_(n) ^(tr),Q_(n-1) ^(tr) is inputted to the demodulator 109 as depicted in FIG. 4.The demodulator 109 comprises a pair of multipliers 400 and 401 to crossmultiple the four truncated inputs by multiplying I_(n) ^(tr), byQ_(n-1) ^(tr) and Q_(n) ^(tr) by I_(n-1) ^(tr). The demodulator 109 alsoincludes an adder 402 arranged to add the outputs from the multipliers.After summing by the adder, The demodulator output is:

x _(n) =Q _(n) ^(tr) I _(n-1) ^(tr) −Q _(n-1) ^(tr) I _(n) ^(tr) =A ²sin(2πΔ_(f) T _(s)+Δφ).   (3)

[0032] where, $T_{s} = \frac{T_{b}}{K}$

[0033] is the sampling duration, Δφ=φ((nT_(s))−φ((n−1)T_(s)) representsthe phase difference during a sampling period. The presence of frequencyoffset, Δ_(f), degrades the overall system performance. Under idealconditions, the frequency offset Δ_(f)=0, the expectation value of thedemodulator output is A² sin Δφ. However, in practice, the frequencyoffset Δ_(f) is always non-zero. From Eqn(3), it can be seen that thedemodulator output x_(n) has been distorted by the frequency offset.When 2πΔ_(f)T_(s) is small, the expression of Eqn(3) can be approximatedby:

x_(n)≈A²(2πΔ_(f)T_(S) cos Δφ+sin Δφ)   (4)

[0034] The expectation value of x_(n) in Eqn(4) is:

E[x _(n) ]=A ²(2πΔ_(f) T _(S) E[cos Δφ]+E[sin Δφ])   (5)

[0035] Under the assumption of equally distributed input data, it can beseen that E[sin Δφ]=0. From Eqn(5), the frequency offset produces a lowfrequency signal A² 2πΔ_(f)T_(s) cos Δφ at the output of the demodulator109. A reference signal for the following decider 111 needs to benon-zero to compensate the frequency offset. A filtering device 110, ablock diagram of the structure and a flow chart of the operation ofwhich are respectively depicted in FIGS. 5 and 6, provides a mechanismfor tracking and filtering the low frequency signal caused by thefrequency offset.

[0036] In the prior art, such as U.S. Pat. No. 5,448,594, entitled“One-bit Differential Demodulator”, a low pass filter is designed totrack the low frequency signal A²2πΔ_(f)T_(s) cos Δφ directly. Thedisadvantage of this method is that if the bandwidth of the filter isexcessive, the resultant output will contain too much high frequencycontent, which endangers the proper operation of the differentialdetector. If the bandwidth of the filter is insufficient, a long time isneeded to capture the burst data. Instead of tracking the low frequencycomponent directly, in the present invention, the envelope of thedemodulator output x_(n) is tracked and low-pass filtered to obtain thelow frequency component. As the envelope of the demodulated signal tendsto be more stable than the demodulated signal itself, a LPF with a muchwider bandwidth can be employed to give a fast tracking withoutintroducing too much disturbance. A separate feature which allows afurther improvement in performance, i.e., capture of the data in ashorter time while keeping a good BER performance simultaneously, is theuse of an adaptive low pass filter. During the beginning of the datareception, the filter can be allowed to begin operation at a widerbandwidth. This is useful in terms of capturing the burst data quickly.As more data is received, the bandwidth of the filter is reducedgradually in order to suppress the high frequency components.

[0037] The filtering device of the present invention is composed ofthree main functional blocks: a tracker 500, an adaptive IIR filter 501and a coefficient of Adaptive IIR filter generator 502. Referring FIG.6, at the beginning of the loop, the parameters α, Max, Min and dc arepreset to an appropriate value (e.g., zero), in which parameter α is acoefficient of the IIR filter 501, Max and Min are respectively thevalues of positive and negative peaks of the envelope of the demodulatoroutput x_(n), and dc is the output of the IIR filter 501, i.e., lowfrequency component of the envelope of the demodulator output x_(n). Thevalues of the positive and negative peaks Max, Min of the input signalx_(n) are updated by using tracker 500 based on the following rules:

[0038] if x_(n)<x_(n-1)>x_(n-2) and x_(n-1)>Min+threshold andx_(n-1)<MAX, And if x_(n-1)>Max or x_(n-1)>dc_(n-1), then Max=x_(n-1)

[0039] if x_(n)>x_(n-1)<x_(n-2)and x_(n-1)<Max−threshold andx_(n-1)>−MAX, And if x_(n-1)<Min or x_(n-1)<dc_(n-1), then Min=x_(n-1)

[0040] where, x_(n), x_(n-1), x_(n-2) are samples of the demodulatoroutput at time n, time n-1 and time n-2, respectively. The parameter“threshold” is a user-defined constant reflecting the smallest gapbetween the positive and negative peaks. The parameter “MAX” is also auser-defined constant, wherein the tracked positive and negative peaksare confined within the range (−MAX, MAX). Moreover, “threshod” and“MAX” are proportional to the sampling duration, the modulation indexbeing employed, as well as the amplitude of the input signal.Coefficient of adaptive IIR filter generator 502 adjusts the coefficientα_(n) of the IIR filter 501 at time n to reduce the bandwidth of theadaptive IIR filter. The coefficient α_(n) at time n is reduced as afunction of time, for example,$\alpha_{n} = {{\frac{31}{32}\alpha_{n - 1}} + {\frac{1}{32}*{\frac{1}{256}.}}}$

[0041] The maximum and the minimum values Max,Min and the parameterα_(n) are used as the inputs to the adaptive IIR filter 501 for thecalculation of the low frequency component of the envelope of thedemodulator output x_(n) according to the following equation$\begin{matrix}{{d\quad c_{n}} = {{\left( {1 - \alpha_{n}} \right)d\quad c_{n - 1}} + {\frac{\alpha_{n}}{2}\left( {{Max} + {Min}} \right)}}} & (6)\end{matrix}$

[0042] where, dc_(n) is the low frequency component of the envelope ofthe signal x_(n) at time n, dc_(n-1) is the low frequency component ofthe envelope of the signal x_(n-1) at time n-1, α_(n) is the filtercoefficient at time n.

[0043] The above process is repeated as long as the communication deviceis in operation. The signal dc_(n) is used as an input to a decider 111of FIG. 1 as a reference signal. The decider 111 makes a hard decisionor soft decision to yield a tentative signal {circumflex over (b)}_(n).For a hard decision, the decider 111 can be a comparator which makesdecision according to the following rule:${\hat{b}}_{n} = \left\{ \begin{matrix}{1,} & {x_{n} > {d\quad c_{n}}} \\{0,} & {x_{n} \leq {d\quad c_{n}}}\end{matrix} \right.$

[0044] However, for a soft decision, the decider 111 can be asubtractor, which subtracts the output of the filtering device, dc_(n),from that of the demodulator 109, x_(n), and a comparator, which makesdecision according to the following rule:${\hat{b}}_{n} = \left\{ \begin{matrix}{1,} & {{x_{n} - {d\quad c_{n}}} > 0} \\{0,} & {{x_{n} - {d\quad c_{n}}} \leq 0}\end{matrix} \right.$

[0045] Based on the filtering device, the effect of frequency offset canbe estimated without using a frequency detector or a complex feedbackloop. The symbol timing of the tentative signals {circumflex over(b)}_(n) is recovered by the symbol timing recovery unit 112. Since allthe values after the AD converter are fixed-point data, all calculationscan be implemented by simple logical operations such as shifting,addition, subtraction, XOR and so on. At the same time, the low-IFtopology can be implemented with a high degree of integration and a highperformance.

[0046] With reference to FIGS. 7-10, a second embodiment of a digitalreceiver of the present invention will be explained.

[0047] Referring first to FIG. 7, a digital receiver 2 of the secondembodiment includes an analogue front-end 100, an AD converter 101, apair of mixers 102 and 103, a pair of LPFs 104 and 105, a pair of delayunits 106 and 107, a normalizer 108, a demodulator 700, a filteringdevice 701, a decider 111, and a symbol timing recovery 112. It can beseen that the differences between the digital receiver 1 of FIG. 1 andthe digital receiver 2 of FIG. 7 lie in the structures of theirdemodulators and their filtering devices.

[0048]FIG. 8 is a schematic block diagram illustrating the structure ofthe demodulator 700 of the digital receiver 2 shown in FIG. 7. Comparingthis demodulator 700 with the demodulator 109 of the digital receiver 1,the demodulator 700 of the receiver 2 further comprises means arrangedto normalize the sum from the adder 402 to its signal power, including apair of multipliers 800 and 801 arranged to self-multiply the twocomponent I_(n) and Q_(n), an adder 802 arranged to sum the outputs fromthe pair of multipliers, and a divider 803 arranged to divide the sum(Q_(n) ^(tr) I_(n-1) ^(tr) −Q_(n) ^(tr) I_(n) ^(tr)) from the adder 402with the sum (c′_(n)=(I_(n) ^(tr))²+(Q_(n) ^(tr))²) from the adder 802,yielding: $\begin{matrix}{x_{n} = {\frac{{Q_{n}^{tr}I_{n - 1}^{tr}} - {Q_{n - 1}^{tr}I_{n}^{tr}}}{\left( I_{n}^{tr} \right)^{2} + \left( Q_{n}^{tr} \right)^{2}} = {\sin \left( {{2{\pi\Delta}_{f}T_{S}} + {\Delta \quad \Phi}} \right)}}} & (7)\end{matrix}$

[0049] The sine of the change in phase of the received signal r(t) isobtained and is independent of the signal power. When 2πΔ_(f)T_(s) issmall, the expression of Eqn(7) can be approximated by:

x_(n)≈2πΔ_(f)T_(S) cos Δφ+sin Δφ  (8)

[0050] The expectation value of x_(n) in Eqn(8) yields:

E[x _(n)]=2πΔ_(f) T _(S) E[cos Δφ]+E[sin Δφ]  (9)

[0051] For the reason given in the first embodiment, E[sin Δφ]=0. FromEqn(9), the frequency offset produces a low frequency signal2πΔ_(f)T_(S) cos Δφ at the output of the demodulator 700. The referencesignal for the decider 111 is non-zero due to the frequency offset. Afiltering device 701 is added in FIG. 7 to adaptively track the lowfrequency signal 2πΔ_(f)T_(S) cos Δφ, which is used as the referencesignal for the following decider 111. The detailed structure of thefiltering device 701 is shown in FIG. 9. The difference between thefiltering devices of FIGS. 5 and 9 is that the filtering device 701further comprises a reset signal generator 900 which is used to detectthe start of data transmission and generate a reset signal to initiatethe tracker 500, the adaptive IIR filter 501, and the coefficient ofadaptive IIR filter generator 502, because in order to allow thereceiver to operate properly in a burst mode communication system, it isimportant to determine when the burst data transmission starts. Theinputs to the demodulator 700 are truncated signals, which makes the sumc′_(n) unable to accurately represent the signal power of the receivedsignal. To correct this problem, before detecting the start of the burstdata transmission, the reset signal generator 701 eliminates the effectof the normalizer on the signal power c′_(n) by shifting it according tothe bit position i from the normalizer 108. In this embodiment, thereset signal generator 900 right-shifts the signal power c′_(n) with2(N-i-1) bits. It is apparent to an ordinary person skilled in the artthat other methods can be applied to eliminate the effect of thenormalization, which falls within the protective scope claimed by thisapplication. The reset signal generator 900 further includes a simpleLPF filter which is used to calculate the average value of thede-normalized signal, namely, the signal power c_(n).

[0052]FIG. 10 shows the flow chart of the operation of the filteringdevice 701 of FIG. 9. Prior to the start of data transmission, theparameters α, Max, Min, dc and d should be reset to the pre-definedinitialization values, in which parameter d is the output of the simpleLPF filter of the reset signal generator 900. Then, the signal powerc′_(n) from the demodulator 700 is de-normalized according to the bitposition from the normalizer 108 and low-pass filtered by the resetsignal generator 900 with the form d_(n)=σd_(n-1)+(1−σ)c_(n), where σ isa constant in the range of (0,1), to obtain an average value of thesignal power c_(n). The average value d_(n) of the signal power c_(n) iscompared with its previous value d_(n-1) at the symbol rate to determinethe start of the data transmission. In this embodiment, the averagevalue d_(n) is compared with its weighted previous values γd_(n-kl), inwhich γ represents a weighting factor of d_(n-kl), K is the oversamplingfactor which is defined in Eqn.(3) and I is an integer (I=1,2,3 . . . ).

[0053] Then, the positive and negative peaks of the demodulator outputx_(n) are tracked by tracker 500 based on the following rules:

[0054] if x_(n)<x_(n-1)>x_(n-2) and x_(n-1)>Min+threshold andx_(n-1)<MAX, And if x_(n-1)>Max or x_(n-1)>dc_(n-1), then Max=x_(n-1)

[0055] if x_(n)>x_(n-1)<x_(n-2) and x_(n-1)<Max−threshold andx_(n-1)>−MAX, And if x_(n-1)<Min or x_(n-1)<dc_(n-1), then Min=x_(n-1)

[0056] Since the amplitude of the input signal to the demodulator 700 ofFIG. 8 is normalized, the two pre-determined constants “threshold” and“MAX” are only proportional to the sampling duration, the modulationindex being employed. The maximum and the minimum values Max,Min areused as the inputs to the adaptive IIR filter 501 for the calculation ofthe low frequency component according to the following equation$\begin{matrix}{{d\quad c_{n}} = {{\left( {1 - \alpha_{n}} \right)d\quad c_{n - 1}} + {\frac{\alpha_{n}}{2}{\left( {{Max} + {Min}} \right).}}}} & (10)\end{matrix}$

[0057] The bandwidth of the adaptive IIR filter is reduced gradually byadjusting the coefficient α_(n) in the coefficient of adaptive IIRfilter generator 502. The coefficient α_(n) is reduced as a function oftime, for example,$\alpha_{n} = {{\frac{31}{32}\alpha_{n - 1}} + {\frac{1}{32}*{\frac{1}{256}.}}}$

[0058] The above process is repeated as long as the communication deviceis in operation. The signal dc_(n) is used as an input to a decider 111of FIG. 7 as a reference signal. The decider 111 makes a hard decisionor soft decision to yield a tentative signal {circumflex over (b)}_(n).For a hard decision, the decider 111 can be a comparator which makesdecision according to the following rule:${\hat{b}}_{n} = \left\{ \begin{matrix}{1,} & {x_{n} > {d\quad c_{n}}} \\{0,} & {x_{n} \leq {d\quad c_{n}}}\end{matrix} \right.$

[0059] However, for a soft decision, the decider 111 can be asubtractor, which subtracts the output of the filtering device, dc_(n),from that of the demodulator 109, x_(n), and a comparator, which makesdecision according to the following rule:${\hat{b}}_{n} = \left\{ \begin{matrix}{1,} & {{x_{n} - {d\quad c_{n}}} > 0} \\{0,} & {{x_{n} - {d\quad c_{n}}} \leq 0}\end{matrix} \right.$

[0060] Based on the filter device, the effect of frequency offset can beestimated without using frequency detector and complex feedback loop.The symbol timing of the tentative signals {circumflex over (b)}_(n) isrecovered by the symbol timing recovery unit 112.

[0061] In conclusion, a single-chip digital receiver for a burst modecommunication system has been disclosed. The digital receiver of thepresent invention is suitable for implementation as an ASIC and isinsensitive to frequency offset. The invention should not be restrictedto the present form. For example, although in the disclosure of thepresent invention the decider is shown to directly follow the filteringdevice, it can be modified to follow other elements, such as a phaseoffset compensator which is arranged to compensate the phase offsetexisting in the signals output from the filtering device. Numerousmodifications, changes, variations, substitutions and equivalents willoccur to those skills in the art without departing from the spirit andscope of the present invention as defined by the following claims:

1. A digital receiver, comprising: a frequency converter arranged toconvert a received signal into baseband signals; delay units arranged todelay the baseband signals to provide delayed signals; normalizing meansarranged to truncate the baseband signals and the delayed signals to apredetermined length and provide normalized signals; a demodulatorarranged to demodulate the normalized signals and provide a demodulatedsignal; and frequency offset sensing means arranged to sense an envelopeof the demodulated signal to provide an offset signal indicative of afrequency offset of the received signal.
 2. A digital receiver accordingto claim 1, wherein the normalizing means is arranged to truncate thebaseband signals and the delayed signals by: finding a signal with thelargest absolute value among the baseband signals and the delayedsignals; determining a bit position of most significant bit of thesignal; and truncating each of the baseband signals and the delayedsignals to the pre-determined length dependent upon the bit position. 3.A digital receiver according to claim 2, wherein the baseband signalsand the delayed signals are signed signals.
 4. A digital receiveraccording to claim 3, wherein each of the normalized signals include asign bit of each of the baseband signals and the delayed signals.
 5. Adigital receiver according to claim 2, wherein the pre-determined lengthis so determined that the normalized signals do not degrade theperformance of the receiver.
 6. A digital receiver according to claim 1,wherein the frequency offset sensing means comprises: means arranged totrack the envelope of the demodulated signal to provide an envelopesignal; and filter arranged to low pass filter the envelope signal toprovide the offset signal.
 7. A digital receiver according to claim 6,wherein the filter is an adaptive IIR filter.
 8. A digital receiveraccording to claim 6, wherein the sensing means further comprises afilter coefficient generator arranged to generate and adjust thecoefficient of the filter.
 9. A digital receiver according to claim 8,wherein the filter coefficient generator reduces the filter coefficientas a function of time.
 10. A digital receiver according to claim 9,wherein the filter coefficient generator adjusts the filter coefficientaccording to the following:${\alpha_{n} = {{\frac{31}{32}\alpha_{n - 1}} + {\frac{1}{32}*\frac{1}{256}}}},$

wherein an is the filter coefficient at time n, α_(n-1) is the filtercoefficient at time n-1.
 11. A digital receiver according to claim 1,wherein the demodulator further comprises a power normalizing meansarranged to generate a power signal from the normalized signals andprovide a normalized demodulated signal to the sensing means.
 12. Adigital receiver according to claim 11, wherein the sensing meansfurther comprises: a reset signal generator for detecting the start ofinput data transmission and reset the sensing means.
 13. A digitalreceiver according to claim 12, wherein the reset signal generator isarranged to detect the power signal to detect the start of transmission.14. A digital receiver according to claim 12, wherein the reset signalgenerator further de-normalize the power signal dependent upon the bitposition from the normalizing means.
 15. A digital receiver according toclaim 1, wherein the frequency converter comprises: an analoguefront-end arranged to convert a frequency of the received signal from aradio frequency into a low intermediate frequency to provide a lowintermediate frequency signal.
 16. A digital receiver according to claim15, wherein the frequency converter further comprises: ananalogue-digital converter arranged to analogue-to-digital convert thelow intermediate frequency signal to provide a digital signal; mixersarranged to respectively mix the digital signal respectively with sineand cosine signals to obtain two orthogonal components; and filtersarranged to filter high frequency parts of the two orthogonal componentsto obtain the baseband signals.
 17. A digital receiver according toclaim 1, further comprising: deciding means arranged to decide atentative signal from the demodulated signal and the offset signal. 18.A digital receiver according to claim 17, wherein the deciding meanscomprises a comparator arranged to compare the demodulated signal withthe offset signal to provide the tentative signal.
 19. A digitalreceiver according to claim 17, wherein the deciding means comprises: asubtractor arranged to subtract the offset signal from the demodulatedsignal and provide a difference signal; and a comparator arranged tocompare the difference signal with zero to provide the tentative signal.20. A digital receiver according to claim 17, further comprising asymbol timing recovery arranged to a symbol timing of the tentativesignal.
 21. A digital receiver according to claim 1, wherein the sensingmeans is arranged to track the envelope of the demodulated signal bymaking the following determinations: if x_(n)<x_(n-1)>x_(n-2) andx_(n-1)>Min+threshold and x_(n-1)<MAX, And if x_(n-1)>Max orx_(n-1)>dc_(n-1), then Max=x_(n-1) if x_(n)>x_(n-1)<x_(n-2) andx_(n-1)<Max−threshold and x_(n-1)>−MAX, And if x_(n-1)<Min orx_(n-1)<dc_(n-1), then Min=x_(n-1) where, x_(n),x_(n-1),x_(n-2) aresamples at time n, at time n-1 and at time n-2 of the first inputsignal, respectively, dc_(n-1) is low frequency component of theenvelope of the demodulated signal at time n-1, Max and Min are theenvelope signal which represent negative and positive peaks of theenvelope of the demodulated signal, and threshold and MAX are presetconstants.
 22. A digital receiver according to claim 12, wherein thethreshold and MAX are proportional to a sampling duration, a modulationindex or amplitude of the demodulated signal.
 23. A digital receiveraccording to claim 12, wherein the filter is arranged to calculate thefrequency component of the envelope signal of the form:${d\quad c_{n}} = {{\left( {1 - \alpha_{n}} \right)d\quad c_{n - 1}} + {\frac{\alpha_{n}}{2}\left( {{Max} + {Min}} \right)}}$

where, dc_(n) is a frequency component of the envelope signal at time n,dc_(n-1) is the frequency component of the envelope signal at time n-1,α_(n) is the filter coefficient at time n.
 24. A digital receiver,comprising: a frequency converter arranged to convert a received signalinto baseband signals; delay units arranged to delay the basebandsignals to provide delayed signals; normalizing means arranged totruncate the baseband signals and the delayed signals to a predeterminedlength and provide normalized signals; a demodulator arranged todemodulate the normalized signals and provide a demodulated signal; anda filter arranged to filter the demodulated signal to provide a filteredsignal and wherein the filter is arranged to have a bandwidth whichdecreases as a function of time.